1. Field of the Invention
The present invention relates to memory systems, and more particularly, to a system and apparatus for improving the performance of a memory system.
2. Description of the Prior Art
An examination of a traditional, prior art memory system reveals a serious shortcoming: at any point in a memory cycle, only a small fraction of the total circuitry in the traditional memory system is active. As a result, the address and data buses of the memory chips in the traditional memory system are unnecessarily idle for a substantial period of time. Traditional solutions to this problem are typically expensive and are based on the use of time multiplexing across disjoint banks of memory chips. In the time multiplexing scheme, the individual memory chips are under-utilized, the memory chip addressing logic is complex, and the interleaving techniques performed by this time multiplexing scheme are highly sensitive to addressing patterns in order to achieve efficient use of the buses.
In the traditional memory system, the following READ cycle is typical: A memory cell in a memory array is selected by presenting a row address. The row address is decoded into a 1-of-n signal by a row decoder, and is then re-powered by driver circuits. The re-driven signals select the correct row in the memory array. The selected row in the memory array is read by sense amplifiers. The column address is decoded by a multiplexer to select the appropriate bit(s) from the row. In a write cycle, the column information is used to demultiplex the input data which, in turn, modifies the selected row.
With regard to the READ cycle in the traditional memory system, the locus of control flows through the memory chip leaving circuits idle in its wake. For example, while the memory array is being accessed, the row decoder sets idle. It is only after the end of a complete cycle that the circuits may be re-used.